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ADE7759
PIN CONFIGURATION
RESET 1
DV DD 2
AV DD 3
V1P 4
20
19
18
17
DIN
DOUT
SCLK
CS
V1N 5
ADE7759
16
CLKOUT
V2N 6
V2P 7
TOP VIEW
(Not to Scale)
15 CLKIN
14 IRQ
AGND 8
REF IN/OUT 9
DGND 10
13
12
11
SAG
ZX
CF
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4, 5
6, 7
8
9
10
11
REV. A
Mnemonic
RESET
DV DD
AV DD
V1P, V1N
V2N, V2P
AGND
REF IN/OUT
DGND
CF
Description
Reset Pin for the ADE7759. A logic low on this pin will hold the ADCs and digital circuitry
(including the serial interface) in a reset condition.
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7759.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled to DGND with a 10 m F capacitor in parallel with a ceramic 100 nF capacitor.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7759.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling method.
This pin should be decoupled to AGND with a 10 m F capacitor in parallel with a ceramic 100 nF
capacitor.
Analog Inputs for Channel 1. This channel is intended for use with the di/dt current transducers
such as Rogowski coil, or other current sensors such as shunt or current transformer (CT). These
inputs are fully differential voltage inputs with maximum differential input signal levels of ± 0.5 V,
± 0.25 V, and ± 0.125 V, depending on the full-scale selection—see Analog Inputs section.
Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these
pins with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry. In addi-
tion, an overvoltage of ± 6 V can be sustained on these inputs without risk of permanent damage.
Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs
are fully differential voltage inputs with a maximum differential signal level of ± 0.5 V. Channel 2
also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins
with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry, and an over-
voltage of ± 6 V can be sustained on these inputs without risk of permanent damage.
This pin provides the ground reference for the analog circuitry in the ADE7759, i.e., ADCs and
reference. This pin should be tied to the analog ground plane or the quietest ground reference in
the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing
filters, current and voltage transducers. To keep ground noise around the ADE7759 to a minimum,
the quiet ground plane should be connected to the digital ground plane at only one point. It is
acceptable to place the entire device on the analog ground plane—see Application Information section.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal
value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/ ∞ C. An external reference
source may be connected at this pin. In either case, this pin should be decoupled to AGND with
a 1 m F capacitor in parallel with a 100 nF capacitor.
This provides the ground reference for the digital circuitry in the ADE7759, i.e., multiplier, filters,
and frequency output (CF). Because the digital return currents in the ADE7759 are small, it is
acceptable to connect this pin to the analog ground plane of the system—see Application Information
section. However, high bus capacitance on the DOUT pin may result in noisy digital current that
affects performance.
Calibration Frequency Logic Output. The CF logic output gives Active Power information. This
output is intended to be used for operational and calibration purposes. The full-scale output fre-
quency can be adjusted by writing to the APGAIN, CFNUM, and CFDEN registers—see Energy
to Frequency Conversion section .
–7 –
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